Conventional methods of fabricating integrated electronic circuits set all internal circuit connections during the manufacturing process. However, because of high development costs and high manufacturing tooling costs of such circuits, new designs are emerging that permit a user to configure or program integrated circuits for specific applications in the field after their purchase. Such circuits are called user-programmable circuits, and they permit a user to program the electrical connections of the circuit by either selectively opening or closing a series of programmable links. The programmable links are electrical interconnects that are electronically forced electrically open or closed at selectable nodes in the circuit by the user after the integrated circuit has been packaged.
An antifuse, which is one type of programmable link, permits a user to program the integrated circuit by creating a short between two conductors to which the original open antifuse connects. Antifuses consist typically of two conductor or semiconductor elements that have a dielectric or insulating material sandwiched between them. During programming, the dielectric is broken down at selected points between the conductive elements by a current developed from a predetermined programming voltage applied to the conductive elements of selected links. This electrically connects the conducting or semiconducting elements to the conductive elements.
One type of user programmable circuit known as a field programmable gate array (hereinafter FPGA) uses an interlayer of amorphous silicon (hereinafter .alpha.-Si) sandwiched between two metal layers. Refractory metals such as titanium tungsten (TiW), tungsten (W), or titanium nitride (TiN) are prime examples of the metals used to sandwich the .alpha.-Si.
Two previously developed antifuse structures include a via antifuse and a mesa antifuse. In a via antifuse, a layer of .alpha.-Si is deposited into a via formed in a dielectric. The .alpha.-Si contacts a metal layer at the bottom of the via with the metal layer forming the bottom of the antifuse or FBOT. Outwardly from the layer of .alpha.-Si in the via is deposited a second metal layer forming the top or FTOP of the antifuse. Previously developed via antifuses have the disadvantage of requiring the via to be relatively shallow, with a large opening so that a uniform .alpha.-Si layer can be formed in the via. A uniform or planarized .alpha.-Si antifuse layer is required to ensure that the breakdown voltage of the antifuse is uniform and to minimize leakage current from the antifuse. If the .alpha.-Si layer is nonuniform, then the breakdown voltage across a semiconductor device including multiple antifuses may be nonuniform making programming and use of the device very difficult.
Therefore, one approach to avoid non-uniform breakdown voltages and leakage currents in antifuses has been to make the vias shallow. Shallow via antifuses, however, require a thin interlayer oxide which results in high interconnect capacitance. As capacitance of the circuit increases, the speed of the circuit decreases. Therefore, shallow via antifuses have the disadvantage of resulting in slow circuits. Moreover, a thin interlayer oxide is susceptible to high electric-field breakdown.
Additionally, the need to put more antifuses in less area requires narrowing the via opening. Narrowing the via opening makes depositing a uniform layer of .alpha.-Si in the via more difficult. Depositing a uniform layer of .alpha.-Si in a narrow via is complicated by increasing the ratio of the distance between antifuse metal layers to the diameter of the via opening, i.e., the aspect ratio of the via antifuse.
FIG. 1 depicts the problems associated with depositing .alpha.-Si in a narrow deep via or via with a high aspect ratio. FIG. 1 includes a portion of via antifuse 10. Via antifuse 10 is formed from first multi-level oxide (MLO1) layer 12 with first barrier metal (MET1) layer 14 formed outwardly from MLO1 layer 12. Formed outwardly from MET1 layer 14 is second multi-level oxide (MLO2) layer 16 including via 18 formed therein. Deposited in via 18 is .alpha.-Si layer 20.
Via 18 of antifuse 10 of FIG. 1 has a high aspect ratio because the ratio of depth 22 to width 24 of via 18 is high. As the aspect ratio increases, the propensity for an uneven .alpha.-Si layer 20 on the bottom of the antifuse or FBOT 26 increases. FBOT 26 of antifuse 20 is shown with cusp 28 in .alpha.-Si layer 20 where the thickness of .alpha.-Si layer 20 at middle 30 is greater than at end points 32 of cusp 28. This nonuniformity in .alpha.-Si layer 20 results in a nonuniform breakdown voltage at which antifuse 10 is programmed and a nonuniform leakage current from antifuse 10. Therefore, as depth 22 increases and/or diameter 24 decreases for via 18, the propensity for cusping in antifuse 10 of FIG. 1 increases. This, in turn, results in a less reliable device.
Therefore, in previously developed via antifuses, a tradeoff is made between the uniformity of the .alpha.-Si layer and the interconnect capacitance of the antifuse. Also, via antifuses presently available are not scalable to accommodate decreasing design geometries.
A second type of antifuse structure presently practiced is the mesa or stack antifuse. In a mesa or stack antifuse, an FBOT metal layer is deposited outwardly from a first metal layer, and a layer of .alpha.-Si is deposited outwardly from the FBOT metal layer. An FTOP metal layer is then formed outwardly from the .alpha.-Si layer. The FTOP metal layer pattern is then formed and delineated by dry etching. A stack antifuse of a desired dimension is then patterned on the FTOP metal structure and formed by etching off the FTOP/.alpha.-Si/FBOT layers of the metal layer. A planarized MLO layer of a desired thickness is then formed over the stack antifuse structure. A via contact is then aligned to the antifuse and etched to expose the antifuse. A second metal layer (MET2) then connects the antifuse through the via contact hole.
In the stack antifuse structure, the alignment of the via contact requires that the antifuse dimension be enlarged to accommodate for the tolerance of alignment registration. This results not only in a higher antifuse capacitance, but also greatly limits the ability of the antifuses to be integrated into densely-packed semiconductor circuits.